Staff Engineer Functional Verification & Methodology (f/m/div)

Responsibilities

• Create and define verification plans.
• Develop the verification environment for our ICs using Universal Verification Methodology (UVM).
• Implement test scenarios using System Verilog and verify functionality using the constrained-random approach.
• Develop assertions in System Verilog for formal verification.
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies.
• Enhance our pool of state-of-the-art verification methods.
• Provide proactive support to internal stakeholders of our verification flow environment.

Qualifications

• A university degree in Electrical Engineering, Computer Science or similar.
• At least 3 years of experience in Metric Driven Verification (digital and mixed signal).
• Capabilities and experience in working with microcontroller-based ICs, as well as with security and safety requirements.
• Excellent know-how with UVM, especially using System Verilog.
• Experience in technical leadership is a plus.
• Knowledge in RTL design and firmware.
• Excellent communication skills in English, German is a bonus.

About Infineon

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

Benefits

• Salary: Minimum 0 EUR, Maximum 0 EUR

Additional Information

• Remote Model: N
• Country Code: de